Get2Chip Launches DesignZone

SAN JOSE, Calif.--(BUSINESS WIRE)--Sept. 16, 2002--Get2Chip(TM) Inc., supplier of high-performance system-on-chip (SOC) synthesis, today expanded its website to include an educational section deemed "DesignZone(TM)" where designers of large integrated circuits (ICs) can download real-world design examples using various implementation paths.

Designers will find design case studies from different application domains, including digital signal processing (DSP), networking and wireless, that detail how to design above the register transfer level (RTL). These designs have been modeled at the architectural abstraction level using the POCA(TM) (Pins-out Cycle-accurate) style of the Verilog hardware description language (HDL). They are automatically synthesized to technology gates using Get2Chip's Architectural Compiler, G2C-AC(TM), which embeds production-proven Global Focused RTL Synthesis technology to achieve high-speed, high-performance synthesis of multi-million gate ICs.

Get2Chip's popular RTL synthesis product G2C-RC(TM) has become the tool of choice for high-performance designs. It has raised the bar for RTL synthesis market in speed, capacity and quality of results.

Remarks Bernd Braune, Get2Chip president and chief executive officer (CEO): "Leading-edge designers are using Get2Chip's G2C-RC on 100 million-plus transistor designs. As we move to 90nm process technology, IC designers will be compelled to design above RTL to meet project constraints, a trend we've already observed. DesignZone is meant to help ease the transition from RTL to higher-level abstraction."

Designs currently posted in the DesignZone include Embedded Zero-Tree Wavelet Encoding (EZW), Ethernet MAC and Triple-Data Encryption (3DES). Designs were initially coded in C and validated, then converted into IO cycle accurate Verilog and validated against the same stimuli at the architectural level.

Each case study includes a primer on the application design example and discusses implementation-related considerations and decisions made when coding the design. Downloadable packages consist of a C package (C Code and Testbench) and a Verilog Package (Verilog Code, Testbench, Synthesis Scripts).

Examples can be downloaded at no charge from the Get2Chip website located at: http://www.get2chip.com/docs/designzone/design_zone.asp.

About Get2Chip

Get2Chip, Inc., is a leading supplier of software products that enable the design of the world's most complex integrated circuits (ICs), primarily found in the communications, wireless, computer, and consumer product markets. It was launched in 2000 by semiconductor veterans and chip design tool experts from Cadence Design Systems, Inc. (NYSE: CDN), LSI Logic Corporation (NYSE: LSI), Mentor Graphics Corporation (Nasdaq: MENT), Synopsys (Nasdaq: SNPS) and VLSI Technology -- now part of Philips Semiconductors (NYSE: PHG, AEX: PHI). Its breakthrough front-end tool suite provides fully integrated, multi-level synthesis that offers the flexibility to do chip design at the architectural, register transfer (RTL) or gate level. Get2Chip's products run on Sun and Hewlett Packard, and PC under Linux. Get2Chip is privately held and has development centers in San Jose, Calif., and Munich, Germany. Corporate headquarters: 2107 North First Street, Suite 350, San Jose, Calif. 95131. Telephone: (408) 501-9600. Facsimile: (408) 501-9610. Email: info@get2chip.com. Web Site: http://www.get2chip.com.

Get2Chip, G2C-AC, G2C-RC and RTL Compiler are trademarks of Get2Chip. All other product and company names are trademarks and registered trademarks of their respective companies.

     Public Relations for Get2Chip
     Nanette Collins, 617/437-1822
     nanette@nvc.com